sky130_fd_sc_ms__dfstp

Delay flop, inverted set, single output

This is a stub of cell description file

  • Cell name: sky130_fd_sc_ms__dfstp

  • Type: cell

  • Verilog name: sky130_fd_sc_ms__dfstp

  • Library: sky130_fd_sc_ms

  • Inputs: 3 (CLK, D, SET_B)

  • Outputs: 1 (Q)

sky130_fd_sc_ms__dfstp symbols

../../../../../_images/sky130_fd_sc_ms__dfstp.symbol.svg
../../../../../_images/sky130_fd_sc_ms__dfstp.pp.symbol.svg

sky130_fd_sc_ms__dfstp schematic

../../../../../_images/sky130_fd_sc_ms__dfstp.schematic.svg

sky130_fd_sc_ms__dfstp GDSII layouts

../../../../../_images/sky130_fd_sc_ms__dfstp_1.svg

sky130_fd_sc_ms__dfstp_1

../../../../../_images/sky130_fd_sc_ms__dfstp_2.svg

sky130_fd_sc_ms__dfstp_2

../../../../../_images/sky130_fd_sc_ms__dfstp_4.svg

sky130_fd_sc_ms__dfstp_4