sky130_fd_sc_ms__dfstp¶
Delay flop, inverted set, single output
This is a stub of cell description file
Cell name: sky130_fd_sc_ms__dfstp
Type: cell
Verilog name: sky130_fd_sc_ms__dfstp
Library: sky130_fd_sc_ms
Inputs: 3 (CLK, D, SET_B)
Outputs: 1 (Q)