File Types

File Type	What does it do?	Open Tooling Options				Closed Tooling Options
		Tool	Status	File format	Source	Tool	Status	File format	Source
Parameterized Cell Generators	Primitive devices that have layouts determined by parameterization.	Magic	Ready	TCL script	Hand Written	Cadence Virtuoso	In Progress	Cadence PCells	Hand Written
DRC Deck	Verifies a design meets the design rules	Magic	Ready	Magic techfile	Hand Written	Mentor Calibre	In progress	SVRF Rule Decks	Generated from documentation data
LVS Deck	Verifies layout and schematic are equivalent.	Magic	Ready	Magic techfile	Hand Written	Mentor Calibre	In progress	SVRF Rule Decks	Generated from documentation data
		Netgen	Ready	Netgen setup file	Hand Written
GDS Generator	Creates mask layout data.	Magic	Ready	Magic techfile	Hand designed
Library Exchange Format Macros	Abstract cell view.	Magic	Ready	LEF	Generated from GDS data	?
Timing Files	Describes pin-to-pin timing	?	Ready	Liberty	Generated from JSON data	?
Netlists	Transistor level circuit description	Ngspice	Ready	Ngspice or CDL	?	?	?	OpenAccess?	Generated from spice files
Device Models	Models for use with SPICE	Ngspice	Ready	SPICE simulation file	?	Cadence Spectre	In Progress	Spectre?	Generated from spice files
Schematic	Transistor level circuit description	Xcircuit?	None	EDIF	?	Cadence Virtuoso	In Progress	OpenAccess?	?
Schematic Symbol	Symbol for use in schematics	Xcircuit?	None	EDIF	?	Cadence Virtuoso	In Progress	OpenAccess?	?
Verilog testbench	Digital simulation	Icarus Verilog	Ready	Verilog	ngsim	Cadence ?	?	OpenAccess?	Generated from Verilog files
XSPICE	Mixed-signal simulation	Ngspice	Ready	SPICE	?	?	?	?	?
	Rules for scribe lines and saw lines	?	None	Unknown	?	Cadence ?	In Progress	Cadence SKILL script	Hand written
Parameterized Cell	Rules for seal ring	Magic	Ready	TCL script	?	Cadence ?	In Progress	Cadence SKILL script	Hand written
	Fill structure rules	Magic	None	Magic techfile	?	Cadence ?	In Progress	Cadence SKILL script	Hand written