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SkyWater SKY130 PDK 0.0.0-369-g7198cf6 documentation
Physical & Design Verification
Layout verse Schematic (LVS) Verification

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SkyWater SKY130 PDK

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Versioning Information
- Current Status
- Version Number Format
Current Status
Known Issues
- Documentation
- PDK Contents Issues
  - Tooling Compatibility
    
    Cadence Virtuoso Support
    
    Mentor Calibre Support
- Specific Libraries
- Design Rule Checking
  - Using Mentor Calibre
  - Using Magic
- Scripts and PDK Tooling
Design Rules
- Background
- Masks
- Criteria & Assumptions
- Layers Reference
- Device and Layout vs. Schematic
- Summary of Key Periphery Rules
- Periphery Rules
  - (x.-)
  - (dnwell.-)
  - (nwell.-)
  - (pwbm.-)
  - (pwdem.-)
  - (hvtp.-)
  - (hvtr.-)
  - (lvtn.-)
  - (ncm.-)
  - (difftap.-)
  - (tunm.-)
  - (poly.-)
  - (rpm.-)
  - (varac.-)
  - (photo.-)
  - (npc.-)
  - (n/ psd.-)
  - (licon.-)
  - (li.-.-)
  - (ct.-)
  - (capm.-)
  - (vpp.-)
  - (m1.-)
  - (via.-)
  - (m2.-)
  - (via2.-)
  - (m3.-)
  - (via3.-)
  - (nsm.-)
  - (indm.-)
  - (m4.-)
  - (via4.-)
  - (m5.-)
  - (pad.-)
  - (rdl.-)
  - (mf.-)
  - (hvi.-)
  - (hvnwell.-)
  - (hvdifftap.-)
  - (hvpoly.-)
  - (hvntm.-)
  - (denmos.-)
  - (depmos.-)
  - (extd.-)
  - (hv.-.-)
  - (vhvi.-.-)
  - (uhvi.-.-)
  - (ulvt-.-)
  - (pwres.-.-)
  - (rfdiode.-.-)
- WLCSP Rules
- High Voltage Methodology
  - Failure Mechanisms in High Voltage Devices
  - High Voltage Implementation Methodology
- Very High Voltage Methodology
  - Failure Mechanisms in VHV Devices
  - VHV Implementation Methodology
- Antenna Rules
  - Definitions
  - Tables
- Parasitic Layout Extraction
  - Resistance Rules
  - Resistance Values
  - Capacitance Rules
  - Capacitance Values
    
    Basic Capacitance - Fringe Downward
    
    Basic Capacitance - Fringe Upward
    
    Basic Capacitance - Parallel
  - Discrepencies
- Device Details
  - 1.8V NMOS FET
    
    Spice Model Information
    
    Details
  - 1.8V low-VT NMOS FET
    
    Spice Model Information
    
    Details
  - 1.8V PMOS FET
    
    Spice Model Information
    
    Details
  - 1.8V low-VT PMOS FET
    
    Spice Model Information
    
    Details
  - 1.8V high-VT PMOS FET
    
    Spice Model Information
    
    Details
  - 1.8V accumulation-mode MOS varactors
    
    Spice Model Information
    
    Details
  - 3.0V native NMOS FET
    
    Spice Model Information
    
    Details
  - 5.0V native NMOS FET
    
    Spice Model Information
    
    Details
  - 5.0V/10.5V NMOS FET
    
    Spice Model Information
    
    Details
  - 5.0V/10.5V PMOS FET
    
    Spice Model Information
    
    Details
  - 10V/16V PMOS FET
    
    Spice Model Information
    
    Details
  - 11V/16V NMOS FET
    
    Spice Model Information
    
    Details
  - 20V NMOS FET
    
    Spice Model Information
    
    Details
  - 20V native NMOS FET
    
    Spice Model Information
    
    Details
  - 20V zero-VT NMOS FET
    
    Spice Model Information
    
    Details
  - 20V isolated NMOS FET
    
    Spice Model Information
    
    Details
  - 20V PMOS FET
    
    Spice Model Information
    
    Details
  - ESD NMOS FET
    
    Spice Model Information
    
    Details
  - Diodes
    
    Spice Model Information
    
    Details
  - Bipolar NPN transistor
    
    Spice Model Information
    
    Details
  - Bipolar PNP transistor
    
    Spice Model Information
    
    Details
  - SRAM cells
    
    Details
    
    Spice Model Information
    
    Spice Model Information
    
    Spice Model Information
  - SONOS cells
  - Generic resistors
  - P+ poly precision resistors
    
    Spice Model Information
    
    Details
  - P- poly precision resistors
    
    Spice Model Information
    
    Details
  - MiM capacitors
    
    Spice Model Information
    
    Details
  - Vertical Parallel Plate (VPP) capacitors
    
    Spice Model Information
    
    Details
- Error Messages
PDK Contents
- Libraries
  - Library Naming
  - Creating New Libraries
  - Primitive Libraries
    
    Foundry provided
  - Digital Standard Cell Libraries
    
    Foundry provided Digital Standard Cell Libraries
    
    Third party provided Digital Standard Cell Libraries
  - Build Space Libraries
    
    Foundry provided Build Space Libraries
  - IO and Periphery Libraries
    
    Foundry provided IO and Periphery Libraries
    
    Third party provided IO and Periphery Libraries
- File Types
Analog Design
Digital Design
Simulation
Physical & Design Verification
- Automated Design Rule (DRC) Checking
- Layout Versus Schematic (LVS) Checking
- Parasitic Extraction (PEX)
- TODO: Calibre Decks
- TODO: MAGIC Decks
Python API
- skywater_pdk package
  - Submodules
  - skywater_pdk.base module
    
    Cell
    
    Library
    
    LibraryNode
    
    LibrarySource
    
    LibraryType
    
    LibraryVersion
    
    parse_filename()
    
    parse_pathname()
  - skywater_pdk.corners module
    
    Corner
    
    CornerFlag
    
    CornerType
    
    OptionalTuple
    
    parse_filename()
  - skywater_pdk.sizes module
    
    CellSize
    
    CellSizeLowPower
    
    CellSizeMinimum
    
    CellSizeNumeric
    
    InvalidSuffixError
    
    parse_size()
  - skywater_pdk.utils module
    
    OrderedFlag
    
    comparable_to_none()
    
    dataclass_json_passthru_config()
    
    dataclass_json_passthru_sequence_config()
    
    extract_numbers()
    
    sortable_extracted_numbers()
  - Module contents
Previous Nomenclature
Glossary
How to Contribute
- Contributor License Agreement
- Code reviews
- Community Guidelines
  - Resolve peacefully
  - Reporting problems
Partners
References

Show Source

TODO: verification/lvs/klayout¶

Previous TODO: verification/lvs/magic

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