:cell:`sky130_fd_sc_ms__dfstp`
==============================

**Delay flop, inverted set, single output**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_ms__dfstp`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_ms__dfstp
-  **Library**: sky130_fd_sc_ms
-  **Inputs**:  3 (CLK, D, SET_B)
-  **Outputs**: 1 (Q)

:cell:`sky130_fd_sc_ms__dfstp` symbols
--------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_ms__dfstp.symbol.svg
      -
      - .. figure:: sky130_fd_sc_ms__dfstp.pp.symbol.svg

:cell:`sky130_fd_sc_ms__dfstp` schematic
----------------------------------------

.. figure:: sky130_fd_sc_ms__dfstp.schematic.svg
    :align: center

:cell:`sky130_fd_sc_ms__dfstp` GDSII layouts
--------------------------------------------



.. figure:: sky130_fd_sc_ms__dfstp_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ms__dfstp_1


.. figure:: sky130_fd_sc_ms__dfstp_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ms__dfstp_2


.. figure:: sky130_fd_sc_ms__dfstp_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ms__dfstp_4