Summary of Key Periphery Rules

Table 23 Table F3a: Front end layers (Low Voltage Devices)

Layer	CD	nwell		diff		tap		n/psdm		poly		npc		licon	Manual
Parameter	width	spc	enc	spc	enc	spc	enc	spc	enc	spc	enc	spc	enc	spc	merge ?
nwell	0.840	1.270	X	X	X	X	X	X	X	X	X	X	X	X	Yes
diff	0.150	0.340	0.180	0.270	X	X	X	X	X	X	X	X	X	X
tap	0.150	0.130	0.180	0.270		0.270	X	X	X	X	X	X	X	X
n/psdm	0.380			0.130	0.130	0.130	0.130	0.380	X	X	X	X	X	X	Yes
poly on diff	0.150					0.300				0.210	X	X	X	X
poly on field	0.150			0.075		0.055				0.210	X	X	X	X
npc	0.270									0.090	X	0.270	X	X	Yes
licon	0.170				0.04/ 0.06		0.000			0.055		0.090		0.170
poly_licon	0.170			0.190	illegal	0.190	illegal				0.080		0.100	0.170

Table 24 Table F3b: Front end layers (High Voltage Devices)

Layer	CD	nwell		diff		tap		poly		lvom		Manual
Parameter	width	spc	enc	spc	enc	spc	enc	spc	enc	spc	enc	merge ?
hnwell	0.840	2.000	X	X	X	X	X	X	X	X	X	Yes
hvi	0.600	0.700		0.180	0.180	0.180	0.180			0.700	X	Yes
hdiff	0.290	0.430	0.330	0.300	X	X	X	X	X	X	X
htap	0.150	0.430	0.330			0.270	X	X	X	X	X
HV poly	0.500			0.075		0.055		0.210	X

Manual merge means that features below min. space should be manually merged by drawing.

Table 25 Table F3c: Back end layers for S8D* flow

Layer	CD	licon		li1		mcon		metal1		via		metal2		via2		metal3
Parameter	width	spc	enc	spc	enc	spc	enc	spc	enc	spc	enc	spc	enc	spc	enc	spc	enc
li1	0.170	undefined	0.000	0.170	X	X	X	X	X	X	X	X	X	X	X	X	X
mcon	0.170				0.000	0.190	X	X	X	X	X	X	X	X	X	X	X
metal1	0.140						0.03/ 0.06	0.140	X	X	X	X	X	X	X	X	X
via	0.150								0.055 / 0.085	0.170	X	X	X	X	X	X	X
metal2	0.140										0.055 / 0.085	0.140	X	X	X	X	X
via2	0.280												0.040	0.280	X	X	X
metal3	0.360														0.045 / 0.07	0.360	X
	All enclosures in tables are nominal and do not apply to butting edges or corners.

Table 26 Table F3d: Back end layers for S8T* flow

Layer	CD	licon		li1		mcon		metal1		via		metal2		via2		metal3
Parameter	width	spc	enc	spc	enc	spc	enc	spc	enc	spc	enc	spc	enc	spc	enc	spc	enc
li1	0.170	undefined	0.000	0.170	X	X	X	X	X	X	X	X	X	X	X	X	X
mcon	0.170				0.000	0.190	X	X	X	X	X	X	X	X	X	X	X
metal1	0.140						0.03/ 0.06	0.140	X	X	X	X	X	X	X	X	X
via	0.150								0.055 / 0.085	0.170	X	X	X	X	X	X	X
metal2	0.140										0.055	0.140	X	X	X	X	X
via2	0.280												0.190	1.200	X	X	X
metal3	2.500														0.310	2.500	X
	All enclosures in tables are nominal and do not apply to butting edges or corners.

Table 27 Table F4: Connectivity of Drawn and Mask Layers [1]

	Deep N Well	N Well	Diff	Tap	Poly	Li1	Capm	Met1	Met2	Met3	Met4	Met5	rdl
Deep N Well	N/A
N Well	Over	N/A
Diff	X	X	N/A
Tap	X	Over	X	N/A
Poly	X	X	X	X	N/A
Li1	X	X	Licon1	Licon1	Licon1 AND Npc	N/A
Capm	X	X	X	X	X	X	N/A
Met1	X	X	X	X	X	Mcon	X	N/A
Met2	X	X	X	X	X	X	X	Via	N/A
Met3	X	X	X	X	X	X	Via2	X	Via2	N/A
Met4	X	X	X	X	X	X	X	X	X	Via3	N/A
Met5	X	X	X	X	X	X	X	X	X	X	Via4	N/A
rdl	X	X	X	X	X	X	X	X	X	X	X	(pad AND pmm) for s8pir/s8pr2-10r flows [1]	N/A
bump	X	X	X	X	X	X	X	X	X	X	X	X	pi2 AND ubm

Footnotes

[1] (1,2)

All layers drawn except pmm which is created as cpmm:mask over bond pads or converted into cpbo:mask.

[2]

Entries in this table show the layer (or combination of layers) that act as connecting layers listed in the row/column headings. An X indicates that there is no direct connection between these layers. N/A is entered along the diagonal. Over is entered along layers contacted by overlapping. A layer is always connected to itself.

[3]

(Met5 AND pad AND rdl) should have one of the following sizes for LVS to work with WLCSP option: 60x60, 50x70, 60x80, and 80x80

Table 28 Table F5: Device Connectivity Table

Devices	LVS	Latch up		Soft
Transistors	open	open		open
resistor	open	open		open
diode	open	open		open
pnp	open	open		open
Inductor	open	short		open
capacitors	open	open		open