Parasitic Layout Extraction¶
This table list layers and contacts included in SPICE models, and parasitic layers include in the AssuraLayout Extraction.
The modeled columns indicate sheets and contacts that are parasitic resistance/capacitance included in the model extraction measurements.
The CAD columns indicate sheets and contacts that are parasitics included in the schematic/layout RCX from Assura.
Name |
Description |
Model Structure |
Modeled RX |
Actual CAD RX |
RX Discrepancy |
Modeled CX |
Actual CX |
CX Discrepancy |
|||
---|---|---|---|---|---|---|---|---|---|---|---|
Notes |
Contacts |
Sheets |
Contacts |
Sheets |
Sheet |
Sheet |
|||||
All Periphery FETs |
mXXXX d g s b w l m ad as pd ps nrd nrs |
none |
diff(min) |
licon/mcon/vias |
diff(ext)/poly/li/m1/m2-m3 |
none |
poly/licon/li |
li/m1/m2-m3 |
li-negligible |
||
20V NDEFETs NONISO |
xXXXX d g s b w l m ad as pd ps nrd nrs |
none |
diff(min)/licon |
mcon/vias |
diff(ext)/poly/li/m1/m2-m3 |
none |
poly/licon/li |
li/m1/m2-m3 |
li-negligible |
||
20V NDEFETs ISO |
xXXXX d g s b w l m ad as pd ps nrd nrs |
none |
diff(min)/licon |
mcon/vias |
diff(ext)/poly/li/m1/m2-m3 |
none |
poly/licon/li/sky130_fd_pr__model__parasitic__diode_ps2dn |
li/m1/m2-m3 |
li-negligible |
||
20V PDEFETs |
xXXXX d g s b w l m ad as pd ps nrd nrs |
none |
diff(min)/licon |
mcon/vias |
diff(ext)/poly/li/m1/m2-m3 |
none |
poly/licon/li |
li/m1/m2-m3/sky130_fd_pr__model__parasitic__diode_ps2dn__hv |
li-negligible |
||
Cell FETs |
NOT EXTRACTED FROM LAYOUT |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
N/A |
||
All Diodes |
dXXXX n1 n2 area pj |
licon |
diff |
licon/mcon/vias |
poly/li/m1/m2-m3 |
licon-negligible |
Junction |
li/m1/m2-m3 |
none |
||
RF ESD Diodes |
xesd_XXXX n1 n2 area pj |
licon/mcon/via |
li/m1/m2 |
via2 |
m3 |
none |
li/m1/m2 |
m3 |
none |
||
pnp_05v5 |
Parasitic PNP |
qXXXX nc nb ne ns sky130_fd_pr__pnp_05v5_W0p68L0p68 m |
licon/mcon |
diff/li |
mcon/vias |
li/m1/m2-m3 |
li/mcon-neglible |
na |
li/m1/m2-m3 |
none |
|
Parasitic PNP (5X) |
qXXXX nc nb ne ns sky130_fd_pr__pnp_05v5_W3p40L3p40 m |
licon/mcon |
diff/li |
mcon/vias |
li/m1/m2-m3 |
li/mcon-neglible |
na |
li/m1/m2-m3 |
none |
||
npn_05v0 |
Parasitic NPN |
qXXXX nc nb ne ns sky130_fd_pr__npn_05v5 m |
licon/mcon |
diff/li |
mcon/vias |
li/m1/m2-m3 |
li/mcon-neglible |
na |
li/m1/m2-m3 |
none |
|
res_generic_XXX |
Non-precision Resistors |
rXXXX a b l w m |
none |
sheet layer |
licon/mcon/vias |
none (no sheet resistance where sheet layer & res id layer intersect) |
none |
none |
junction/li/m1/m2-m3 |
parasitic capacitance to substrate (tool limitation) |
|
res_iso_pw |
Isolated Pwell Resistor |
xXXXX pwres r0 r1 b l w m |
licon/mcon |
pwell/li |
vias |
m1/m2-m3 |
none |
none |
junction/m1/m2-m3 |
li-negligible |
|
res_high_XXX |
Precision poly resistor |
xXXXXX hrpoly_X_X r0 r1 b l w m |
licon/mcon |
poly/li |
via |
m1/m2-m3 |
none |
poly-sub |
m1/m2-m3 |
li-negligible |
|
cap_mim_XXXX |
MIM Capacitor (2-terminal) |
xXXXX sky130_fd_pr__cap_mim_m3_2 c0 c1 w l m |
via2 |
m3 |
N/A |
poly/li/m1/m2 |
m2 (of the device) -negligible |
capm-m2 |
li/m1/m2-m3 |
routing layers underneath device |
|
cap_mim_XXXX |
MIM Capacitor (3-terminal) |
xXXXX sky130_fd_pr__model__cap_mim c0 c1 b w l m |
via2 |
m3 |
N/A |
poly/li/m1/m2 |
m2 (of the device) -negligible |
m2-sub/capm-m2 |
|
none |
|
cap_vpp_XXXX |
Vertical Parallel Plate Cap |
xXXXX sky130_fd_pr__cap_vpp_XXXXX c0 c1 b m |
No special RCX implementation for VPP required since black-box LVS will be used |
mcon/via |
li/m1/m2 |
none (black box LVS) |
none (black box LVS) |
none |
li/mcon//m1/via/m2 |
none (black box LVS) |
Parasitic capacitance to routing above |
cap_vpp_XXXX |
Vertical Parallel Plate Cap over MOSCAP |
xXXXX sky130_fd_pr__cap_vpp_XXXXX c0 c1 b m |
mcon/via |
li/m1/m2 |
none (black box LVS) |
none (black box LVS) |
none |
li/mcon//m1/via/m2 |
none (black box LVS) |
Parasitic capacitance to routing above |
|
cap_vpp_XXXX |
4-terminal Vertical Parallel Plate Cap (M3 Shielded) |
xXXXXX sky130_fd_pr__cap_vpp_XXXX c0 c1 b term4 m= |
licon/mcon/via |
poly/li/m1/m2 |
via3/via4 |
m3/m4/m5 |
none |
poly/licon/li/mcon/m1/via/m2/m3 |
m3-substrate (not m3-m2), neighboring metal to VPP metal |
none |
|
cap_vpp_XXXX |
4-terminal Vertical Parallel Plate Cap (M5 Shielded) |
xXXXXX sky130_fd_pr__cap_vpp_XXXX c0 c1 b term4 m= |
licon/mcon/via/via2/via3 |
poly/li/m1/m2/m3/m4 |
via4 |
m5 |
none |
poly/licon/li/mcon/m1/via/m2/m3/m4/m5 |
neighboring metal to VPP metal |
none |
|
cap_vpp_XXXX |
3-terminal Vertical Parallel Plate Cap |
xXXXXX sky130_fd_pr__cap_vpp_XXXX c0 c1 b m= xXXXXX sky130_fd_pr__cap_vpp_XXXX c0 c1 b m= |
mcon/via |
li/m1/m2 |
via2/via3/via4 |
m3/m4/m5 |
none |
li/mcon/m1/via/m2 |
neighboring metal to VPP metal |
Parasitic capacitance to routing above |
|
cap_vpp_XXXX |
3-terminal Vertical Parallel Plate Cap |
xXXXXX sky130_fd_pr__cap_vpp_XXXX c0 c1 b m= |
mcon/via/via2 |
li/m1/m2/m3 |
via3/via4 |
m4/m5 |
none |
li/mcon/m1/via/m2/via2/m3 |
neighboring metal to VPP metal |
none |
|
cap_var_XXXX |
Varactor |
xXXXXX sky130_fd_pr__cap_var_XXXX c0 c1 b l w m |
licon/mcon/via |
diff/poly/li/m1/m2 |
via2 |
m3 |
none |
poly/li/m1/m2 |
nwdiodemodel/m3* |
none |
|
Inductor |
xXXXXX xindXXXX t1 t2 body |
No special RCX implementation for inductor required since black-box LVS will be used |
via |
m2/Cu |
Nothing extracted within inductor.dg layer |
none |
m2/via/Cu |
Nothing extracted within inductor.dg layer |
none |
Note
The models includes M1/M2 capacitance. As a result of RCX extraction limitation M1/M2 routing over the varactor will have no capacitance extraction.
Routing and placement of devices over or under Precision resistors (xhrpoly_X_X) should be avoided.
The parasitic capacitance between 3-terminal MIMC and any routing/devices is not included in layout RCX, except M3 by 1 snap grid width.
No artificial fringing capacitance is extracted for MIMC M2/M3 due to CAD algorithm after CAPM sizing.
The parasitic capacitance between Precision resistors (xhrpoly_X_X) and any routing/devices is not included in layout RCX.
S8Q-5R is not supported for RF ESD diode RCX blocking.
The areaid:substratecut
will be extracted as a 0.123 ohm two terms resistor.
Resistance Rules¶
Todo
This table should be rendered like the periphery rules.
General (RES.-) |
||
.X |
Parasitic resistance is not extrated under a sheet layer with it’s corresponding res.id layer. |
|
Sheet Resistance (SR.-) |
||
.X |
Calibre now extracts deltaW by bucketing the sheet rho based on different widths. |
The accuracy of each bucket must be within 2% of the Sheet Rho Calc using deltaW. |
.met3 |
Parasitic resistance is calculated for all metal3 (if metal3 exists for the specific technology) |
|
.met2 |
Parasitic resistance is calculated for all metal2. |
|
.met1 |
Parasitic resistance is calculated for all metal1 with the exception of varactor which follow rule SR.xcnwvc.1 |
|
.li1 |
Parasitic resistance is calculated for all li1. |
|
.poly.1 |
Parasitic resistance on gates is calculated to the center of the gate. |
|
.poly.2 |
Parasitic resistance for poly is not extracted beyond the device terminal. The device terminal for all devices but MOS is at the edge of the poly. Note: This means that parasitic resistance is not extracted for poly that is part of an LVS capacitor or LVS resistor. The LVS capacitors have poly in the model. |
|
.diff.1 |
Parasitic resistance is not extracted for any diffusion regions. |
|
.diff.2 |
Extract NRD/NRS for MOSFETs (except extendedDrain Fets) per the equations defined in USC-206. NRD/NRS for the n-type ESD devices must include the ntap enclosed in the source/drain ndiff hole NRD/NRS for the p-type ESD devices must include the ptap enclosed in the source/drain pdiff hole. |
|
.xnwvc.1 |
Inside the Varactor device boundry (see rule PASSIVES.cnwvc.1) all layers listed in the model (m1 and below) will not have resistance extracted. |
|
contact-to-gate space (CT.-) |
||
.via |
All vias will have parasitic resistance extracted. |
|
.mcon |
All mcons will have parasitic resistance extracted. |
|
.licon.1 |
All licons that are connected to Poly and not connected to the poly of the xhrpoly_X_X device should have resistance extracted. |
|
.licon.2 |
All licons that are connnected to non-precision resistors will have resistance extracted. |
|
.licon.3 |
All licons that are connected to FETs will be extracted by RCX. |
|
.licon.4 |
All licons on diff of PNP/NPN will be considered part of the device model. |
|
.licon.5 |
All licons on tap of PNP/NPN will be considered part of the device model. |
|
.licon.6 |
All licons on non-PNP tap regions will have parasitic resistance extracted. |
|
.hrpoly.1 |
All licons and mcons that are part of the hrpoly resistor will not have parasitic resitance extracted, these contacts are in the models. |
|
.pwres.1 |
All licons and mcons that are part of the pwell resistor will not have parasitic resitance extracted, these contacts are in the models. |
Resistance Values¶
This section includes tables of basic resistance values for SKY130.
Further data can be found in the “SKY130 Stackup Capacitance Data” spreadsheet.
Layer |
Resistivity (mohms/sq) |
---|---|
Poly |
48200 |
Local interconnect |
12800 |
Metal1 |
125 |
Metal2 |
125 |
Metal3 |
47 |
Metal4 |
47 |
Metal5 |
29 |
Deep nwell |
2200000 |
Pwell (in deep nwell) |
3050000 |
Nwell |
1700000 |
N-diffusion |
120000 |
P-diffusion |
197000 |
HV N-diffusion |
114000 |
HV P-diffusion |
191000 |
XHR poly resistor |
319800 |
UHR poly resistor |
2000000 |
LICON contact |
15000 |
MCON contact |
152000 |
VIA |
4500 |
VIA2 |
3410 |
VIA3 |
3410 |
VIA4 |
380 |
Capacitance Rules¶
Todo
This table should be rendered like the periphery rules.
General (CAP.-) |
||
.X.1 |
No capacitance is extracted due to contacts. (This is a generic layout extraction tool limitation.) |
|
MOS Devices (MOS.-) |
||
.mos.1 |
area between poly and diff should not have capacitance extracted. |
|
.mos.2 |
li within .055um will not have fringing capacitance (npcon.4 = 0.055 for S8) |
|
.mos.3 |
there will be no fringing caps between gates ( as capacitance is shielded by the LICON and MCON). |
|
.mos.4 |
All 20V NMOS ISO DEFETs will have the parasitic diodes included in the models. |
|
.mos.5 |
All 20V NMOS ISO DEFETs will have the parasitic diode included in the models. |
This model also includes the 5th terminal Drain-Psub diode (DeepNwell - Psub). |
.mos.6 |
All 20V PMOS DEFETs will have the parasitic DeepNwell-Psub diode included in the CAD extraction. |
|
.mos.7 |
The only 20V DEFET instance parameter that the model uses from CAD extraction is m-factor. |
The model will over-write all other instance parameters from CAD extraction. |
Resistors (RES.-) |
||
.res.1 |
short devices must not have capacitance calculated across the device. |
|
.res.2 |
fuse devices must have capacitance extracted. |
|
.res.3 |
poly resistors that are not the precision poly resistors (xhrpoly_X_X) must have capacitance extracted. |
|
.res.4 |
metops that are merged must have capacitance extracted. |
|
.res.5 |
parasitic resistors for diff/nwell must have the junction diode extracted. |
|
.res.6 |
Poly precision resistors must not have the poly-psub parasitic capacitance extracted (RCX should also exclude head/tail poly-psub capacitance). |
|
.res.7 |
For Poly precision resistors xhrpoly_X_1, the device recognition layer is defined by growing the poly.rs AND rpm.dg layers 0.50 um(head/tail distance from ID layer) in all directions. Poly-Field/Diff/Well, and Poly-Poly, Poly-Li will not have capacitance extracted inside this device recognition layer. |
|
.res.8 |
For Poly precision resistors xhrpoly_X_2, the device recognition layer is defined by growing the poly.rs AND rpm.dg layers 1.18 um(head/tail distance from ID layer) in all directions. Poly-Field/Diff/Well, and Poly-Poly, Poly-Li will not have capacitance extracted inside this device recognition layer. |
|
Capacitors (PASSIVES.-) |
||
.cnwvc.1 |
capacitance will not be extracted for field, diff, Poly, Li, M1, M2 up to 0.465u away from devicen recognition layer (as defined in LVS table of TDR) |
|
.cmimc.1 |
capacitance will not be extracted between M2 to field, diff, Poly, Li, M1 up to 0.14u away from devicen recognition layer (intersection of M2 overlapping CAPM that’s connected to VIA2, 3-terminal MiM only) |
|
.crfesd.1 |
capacitance will not be extracted for field, diff, Poly, Li, M1, M2 up to 0.4u away from device recognition layers (diode terminals) |
|
.xcmvpp.1 |
|
|
Bipolar Devices |
||
none |
Capacitance Values¶
This section includes tables of basic capacitance values for SKY130.
Further data can be found in the “SKY130 Stackup Capacitance Data” spreadsheet.
Basic Capacitance - Fringe Downward¶
Fringe capacitances are a constant value per unit length and are approximations. Determined by creating a layout with a 5um x 10um rectangle of each layer over or under a much larger rectangle of the other layer. The fringe capacitance computed from the total given minus the parallel plate capacitance.
“downward direction” means that the larger plate is below the 5um x 10um plate.
The layer in the first column is always the layer with the 5um x 10um plate.
Interlayer fringe capacitance (downward direction) (aF/um) |
Poly |
Local interconnect |
Metal1 |
Metal2 |
Metal3 |
Metal4 |
---|---|---|---|---|---|---|
Local interconnect |
51.846 |
|||||
Metal1 |
46.724 |
59.496 |
||||
Metal2 |
41.222 |
46.277 |
67.045 |
|||
Metal3 |
43.531 |
46.708 |
54.814 |
69.846 |
||
Metal4 |
38.105 |
39.709 |
42.563 |
46.382 |
70.522 |
|
Metal5 |
39.908 |
41.147 |
43.188 |
45.592 |
54.152 |
82.819 |
Basic Capacitance - Fringe Upward¶
Fringe capacitances are a constant value per unit length and are approximations. Determined by creating a layout with a 5um x 10um rectangle of each layer over or under a much larger rectangle of the other layer. The fringe capacitance computed from the total given minus the parallel plate capacitance.
“upward direction” means that the larger plate is above the 5um x 10um plate.
The layer in the first column is always the layer with the 5um x 10um plate.
Interlayer fringe capacitance (upward direction) (aF/um) |
Local interconnect |
Metal1 |
Metal2 |
Metal3 |
Metal4 |
Metal5 |
---|---|---|---|---|---|---|
Poly |
25.138 |
16.691 |
11.166 |
9.18 |
6.3505 |
6.4903 |
Local interconnect |
34.7 |
21.739 |
15.078 |
10.141 |
7.6366 |
|
Metal1 |
48.193 |
26.676 |
16.421 |
12.017 |
||
Metal2 |
44.432 |
22.332 |
15.693 |
|||
Metal3 |
42.643 |
27.836 |
||||
Metal4 |
46.976 |
Basic Capacitance - Parallel¶
Interlayer parallel plate capacitance (aF/um^2) |
Local interconnect |
Metal1 |
Metal2 |
Metal3 |
Metal4 |
Metal5 |
---|---|---|---|---|---|---|
Poly |
94.1644 |
44.8056 |
24.4968 |
16.0552 |
10.0131 |
7.2085 |
Local interconnect |
114.1970 |
37.5647 |
20.7915 |
11.6705 |
8.0265 |
|
Metal1 |
133.8610 |
34.5350 |
15.0275 |
9.4789 |
||
Metal2 |
86.1861 |
20.3321 |
11.3410 |
|||
Metal3 |
84.0346 |
19.6269 |
||||
Metal4 |
68.3252 |
Discrepencies¶
- Non-precision poly resistors
These resistors do not extract capacitance to substrate.
This needs to be accounted for manually by using ICPS_0150_0210 (cap per perimeter), and ICPS_2000_4000 (cap per area).
- Un-shielded VPP’s
Any routing above an un-shielded VPP will not be extracted.
The impact of this on total capacitance and parasitic capacitance is already comprehended in the model corners, however, cross-talk is not modeled. Also, parasitic cap is routed to ground and this may not be ideal for the scenario. The parasitic cap can be estimated using RescapWeb.