sky130_fd_sc_ms__clkdlyinv3sd2¶
Clock Delay Inverter 3-stage 0.25um length inner stage gate
This is a stub of cell description file
Cell name: sky130_fd_sc_ms__clkdlyinv3sd2
Type: cell
Verilog name: sky130_fd_sc_ms__clkdlyinv3sd2
Library: sky130_fd_sc_ms
Inputs: 1 (A)
Outputs: 1 (Y)