:cell:`sky130_fd_sc_ms__clkdlyinv3sd2`
======================================

**Clock Delay Inverter 3-stage 0.25um length inner stage gate**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_ms__clkdlyinv3sd2`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_ms__clkdlyinv3sd2
-  **Library**: sky130_fd_sc_ms
-  **Inputs**:  1 (A)
-  **Outputs**: 1 (Y)

:cell:`sky130_fd_sc_ms__clkdlyinv3sd2` symbols
----------------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_ms__clkdlyinv3sd2.symbol.svg
      -
      - .. figure:: sky130_fd_sc_ms__clkdlyinv3sd2.pp.symbol.svg

:cell:`sky130_fd_sc_ms__clkdlyinv3sd2` schematic
------------------------------------------------

.. figure:: sky130_fd_sc_ms__clkdlyinv3sd2.schematic.svg
    :align: center

:cell:`sky130_fd_sc_ms__clkdlyinv3sd2` GDSII layouts
----------------------------------------------------



.. figure:: sky130_fd_sc_ms__clkdlyinv3sd2_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ms__clkdlyinv3sd2_1