sky130_fd_sc_ms__a222o¶
2-input AND into all inputs of 3-input OR
This is a stub of cell description file
Cell name: sky130_fd_sc_ms__a222o
Type: cell
Verilog name: sky130_fd_sc_ms__a222o
Library: sky130_fd_sc_ms
Inputs: 6 (A1, A2, B1, B2, C1, C2)
Outputs: 1 (X)