:cell:`sky130_fd_sc_ms__a222o`
==============================

**2-input AND into all inputs of 3-input OR**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_ms__a222o`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_ms__a222o
-  **Library**: sky130_fd_sc_ms
-  **Inputs**:  6 (A1, A2, B1, B2, C1, C2)
-  **Outputs**: 1 (X)

:cell:`sky130_fd_sc_ms__a222o` symbols
--------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_ms__a222o.symbol.svg
      -
      - .. figure:: sky130_fd_sc_ms__a222o.pp.symbol.svg

:cell:`sky130_fd_sc_ms__a222o` schematic
----------------------------------------

.. figure:: sky130_fd_sc_ms__a222o.schematic.svg
    :align: center

:cell:`sky130_fd_sc_ms__a222o` GDSII layouts
--------------------------------------------



.. figure:: sky130_fd_sc_ms__a222o_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ms__a222o_1


.. figure:: sky130_fd_sc_ms__a222o_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ms__a222o_2