sky130_fd_sc_ls__sdfstp

Scan delay flop, inverted set, non-inverted clock, single output

This is a stub of cell description file

  • Cell name: sky130_fd_sc_ls__sdfstp

  • Type: cell

  • Verilog name: sky130_fd_sc_ls__sdfstp

  • Library: sky130_fd_sc_ls

  • Inputs: 5 (CLK, D, SCD, SCE, SET_B)

  • Outputs: 1 (Q)

sky130_fd_sc_ls__sdfstp symbols

../../../../../_images/sky130_fd_sc_ls__sdfstp.symbol.svg
../../../../../_images/sky130_fd_sc_ls__sdfstp.pp.symbol.svg

sky130_fd_sc_ls__sdfstp schematic

../../../../../_images/sky130_fd_sc_ls__sdfstp.schematic.svg

sky130_fd_sc_ls__sdfstp GDSII layouts

../../../../../_images/sky130_fd_sc_ls__sdfstp_1.svg

sky130_fd_sc_ls__sdfstp_1

../../../../../_images/sky130_fd_sc_ls__sdfstp_2.svg

sky130_fd_sc_ls__sdfstp_2

../../../../../_images/sky130_fd_sc_ls__sdfstp_4.svg

sky130_fd_sc_ls__sdfstp_4