:cell:`sky130_fd_sc_ls__sdfstp`
===============================

**Scan delay flop, inverted set, non-inverted clock, single output**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_ls__sdfstp`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_ls__sdfstp
-  **Library**: sky130_fd_sc_ls
-  **Inputs**:  5 (CLK, D, SCD, SCE, SET_B)
-  **Outputs**: 1 (Q)

:cell:`sky130_fd_sc_ls__sdfstp` symbols
---------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_ls__sdfstp.symbol.svg
      -
      - .. figure:: sky130_fd_sc_ls__sdfstp.pp.symbol.svg

:cell:`sky130_fd_sc_ls__sdfstp` schematic
-----------------------------------------

.. figure:: sky130_fd_sc_ls__sdfstp.schematic.svg
    :align: center

:cell:`sky130_fd_sc_ls__sdfstp` GDSII layouts
---------------------------------------------



.. figure:: sky130_fd_sc_ls__sdfstp_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ls__sdfstp_1


.. figure:: sky130_fd_sc_ls__sdfstp_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ls__sdfstp_2


.. figure:: sky130_fd_sc_ls__sdfstp_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ls__sdfstp_4