sky130_fd_sc_ls__dlxtn¶
Delay latch, inverted enable, single output
This is a stub of cell description file
Cell name: sky130_fd_sc_ls__dlxtn
Type: cell
Verilog name: sky130_fd_sc_ls__dlxtn
Library: sky130_fd_sc_ls
Inputs: 2 (D, GATE_N)
Outputs: 1 (Q)