:cell:`sky130_fd_sc_ls__dlxtn`
==============================

**Delay latch, inverted enable, single output**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_ls__dlxtn`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_ls__dlxtn
-  **Library**: sky130_fd_sc_ls
-  **Inputs**:  2 (D, GATE_N)
-  **Outputs**: 1 (Q)

:cell:`sky130_fd_sc_ls__dlxtn` symbols
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.. list-table:: 

    * - .. figure:: sky130_fd_sc_ls__dlxtn.symbol.svg
      -
      - .. figure:: sky130_fd_sc_ls__dlxtn.pp.symbol.svg

:cell:`sky130_fd_sc_ls__dlxtn` schematic
----------------------------------------

.. figure:: sky130_fd_sc_ls__dlxtn.schematic.svg
    :align: center

:cell:`sky130_fd_sc_ls__dlxtn` GDSII layouts
--------------------------------------------



.. figure:: sky130_fd_sc_ls__dlxtn_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ls__dlxtn_1


.. figure:: sky130_fd_sc_ls__dlxtn_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ls__dlxtn_2


.. figure:: sky130_fd_sc_ls__dlxtn_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ls__dlxtn_4