sky130_fd_sc_ls__dlclkp¶
Clock gate
This is a stub of cell description file
Cell name: sky130_fd_sc_ls__dlclkp
Type: cell
Verilog name: sky130_fd_sc_ls__dlclkp
Library: sky130_fd_sc_ls
Inputs: 2 (GATE, CLK)
Outputs: 1 (GCLK)
Clock gate
This is a stub of cell description file
Cell name: sky130_fd_sc_ls__dlclkp
Type: cell
Verilog name: sky130_fd_sc_ls__dlclkp
Library: sky130_fd_sc_ls
Inputs: 2 (GATE, CLK)
Outputs: 1 (GCLK)