:cell:`sky130_fd_sc_ls__dlclkp`
===============================

**Clock gate**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_ls__dlclkp`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_ls__dlclkp
-  **Library**: sky130_fd_sc_ls
-  **Inputs**:  2 (GATE, CLK)
-  **Outputs**: 1 (GCLK)

:cell:`sky130_fd_sc_ls__dlclkp` symbols
---------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_ls__dlclkp.symbol.svg
      -
      - .. figure:: sky130_fd_sc_ls__dlclkp.pp.symbol.svg

:cell:`sky130_fd_sc_ls__dlclkp` schematic
-----------------------------------------

.. figure:: sky130_fd_sc_ls__dlclkp.schematic.svg
    :align: center

:cell:`sky130_fd_sc_ls__dlclkp` GDSII layouts
---------------------------------------------



.. figure:: sky130_fd_sc_ls__dlclkp_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ls__dlclkp_1


.. figure:: sky130_fd_sc_ls__dlclkp_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ls__dlclkp_2


.. figure:: sky130_fd_sc_ls__dlclkp_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_ls__dlclkp_4