sky130_fd_sc_hs__sdfrtn¶
Scan delay flop, inverted reset, inverted clock, single output
This is a stub of cell description file
Cell name: sky130_fd_sc_hs__sdfrtn
Type: cell
Verilog name: sky130_fd_sc_hs__sdfrtn
Library: sky130_fd_sc_hs
Inputs: 5 (RESET_B, CLK_N, D, SCD, SCE)
Outputs: 1 (Q)