sky130_fd_sc_hs__sdfrtn

Scan delay flop, inverted reset, inverted clock, single output

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hs__sdfrtn

  • Type: cell

  • Verilog name: sky130_fd_sc_hs__sdfrtn

  • Library: sky130_fd_sc_hs

  • Inputs: 5 (RESET_B, CLK_N, D, SCD, SCE)

  • Outputs: 1 (Q)

sky130_fd_sc_hs__sdfrtn symbols

../../../../../_images/sky130_fd_sc_hs__sdfrtn.symbol.svg
../../../../../_images/sky130_fd_sc_hs__sdfrtn.pp.symbol.svg

sky130_fd_sc_hs__sdfrtn schematic

contents/libraries/sky130_fd_sc_hs/cells/sdfrtn/sky130_fd_sc_hs__sdfrtn.schematic.svg

sky130_fd_sc_hs__sdfrtn GDSII layouts

../../../../../_images/sky130_fd_sc_hs__sdfrtn_1.svg

sky130_fd_sc_hs__sdfrtn_1