:cell:`sky130_fd_sc_hs__sdfrtn`
===============================

**Scan delay flop, inverted reset, inverted clock, single output**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hs__sdfrtn`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hs__sdfrtn
-  **Library**: sky130_fd_sc_hs
-  **Inputs**:  5 (RESET_B, CLK_N, D, SCD, SCE)
-  **Outputs**: 1 (Q)

:cell:`sky130_fd_sc_hs__sdfrtn` symbols
---------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_hs__sdfrtn.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hs__sdfrtn.pp.symbol.svg

:cell:`sky130_fd_sc_hs__sdfrtn` schematic
-----------------------------------------

.. figure:: sky130_fd_sc_hs__sdfrtn.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hs__sdfrtn` GDSII layouts
---------------------------------------------



.. figure:: sky130_fd_sc_hs__sdfrtn_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hs__sdfrtn_1