sky130_fd_sc_hs__edfxtp

Delay flop with loopback enable, non-inverted clock, single output

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hs__edfxtp

  • Type: cell

  • Verilog name: sky130_fd_sc_hs__edfxtp

  • Library: sky130_fd_sc_hs

  • Inputs: 3 (CLK, D, DE)

  • Outputs: 1 (Q)

sky130_fd_sc_hs__edfxtp symbols

../../../../../_images/sky130_fd_sc_hs__edfxtp.symbol.svg
../../../../../_images/sky130_fd_sc_hs__edfxtp.pp.symbol.svg

sky130_fd_sc_hs__edfxtp schematic

contents/libraries/sky130_fd_sc_hs/cells/edfxtp/sky130_fd_sc_hs__edfxtp.schematic.svg

sky130_fd_sc_hs__edfxtp GDSII layouts

../../../../../_images/sky130_fd_sc_hs__edfxtp_1.svg

sky130_fd_sc_hs__edfxtp_1