:cell:`sky130_fd_sc_hs__edfxtp`
===============================

**Delay flop with loopback enable, non-inverted clock, single output**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hs__edfxtp`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hs__edfxtp
-  **Library**: sky130_fd_sc_hs
-  **Inputs**:  3 (CLK, D, DE)
-  **Outputs**: 1 (Q)

:cell:`sky130_fd_sc_hs__edfxtp` symbols
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.. list-table:: 

    * - .. figure:: sky130_fd_sc_hs__edfxtp.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hs__edfxtp.pp.symbol.svg

:cell:`sky130_fd_sc_hs__edfxtp` schematic
-----------------------------------------

.. figure:: sky130_fd_sc_hs__edfxtp.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hs__edfxtp` GDSII layouts
---------------------------------------------



.. figure:: sky130_fd_sc_hs__edfxtp_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hs__edfxtp_1