sky130_fd_sc_hs__edfxbp

Delay flop with loopback enable, non-inverted clock, complementary outputs

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hs__edfxbp

  • Type: cell

  • Verilog name: sky130_fd_sc_hs__edfxbp

  • Library: sky130_fd_sc_hs

  • Inputs: 3 (CLK, D, DE)

  • Outputs: 2 (Q, Q_N)

sky130_fd_sc_hs__edfxbp symbols

../../../../../_images/sky130_fd_sc_hs__edfxbp.symbol.svg
../../../../../_images/sky130_fd_sc_hs__edfxbp.pp.symbol.svg

sky130_fd_sc_hs__edfxbp schematic

contents/libraries/sky130_fd_sc_hs/cells/edfxbp/sky130_fd_sc_hs__edfxbp.schematic.svg

sky130_fd_sc_hs__edfxbp GDSII layouts

../../../../../_images/sky130_fd_sc_hs__edfxbp_1.svg

sky130_fd_sc_hs__edfxbp_1