:cell:`sky130_fd_sc_hs__edfxbp`
===============================

**Delay flop with loopback enable, non-inverted clock, complementary outputs**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hs__edfxbp`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hs__edfxbp
-  **Library**: sky130_fd_sc_hs
-  **Inputs**:  3 (CLK, D, DE)
-  **Outputs**: 2 (Q, Q_N)

:cell:`sky130_fd_sc_hs__edfxbp` symbols
---------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_hs__edfxbp.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hs__edfxbp.pp.symbol.svg

:cell:`sky130_fd_sc_hs__edfxbp` schematic
-----------------------------------------

.. figure:: sky130_fd_sc_hs__edfxbp.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hs__edfxbp` GDSII layouts
---------------------------------------------



.. figure:: sky130_fd_sc_hs__edfxbp_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hs__edfxbp_1