sky130_fd_sc_hs__dfxbp

Delay flop, complementary outputs

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hs__dfxbp

  • Type: cell

  • Verilog name: sky130_fd_sc_hs__dfxbp

  • Library: sky130_fd_sc_hs

  • Inputs: 2 (CLK, D)

  • Outputs: 2 (Q, Q_N)

sky130_fd_sc_hs__dfxbp symbols

../../../../../_images/sky130_fd_sc_hs__dfxbp.symbol.svg
../../../../../_images/sky130_fd_sc_hs__dfxbp.pp.symbol.svg

sky130_fd_sc_hs__dfxbp schematic

contents/libraries/sky130_fd_sc_hs/cells/dfxbp/sky130_fd_sc_hs__dfxbp.schematic.svg

sky130_fd_sc_hs__dfxbp GDSII layouts

../../../../../_images/sky130_fd_sc_hs__dfxbp_1.svg

sky130_fd_sc_hs__dfxbp_1

../../../../../_images/sky130_fd_sc_hs__dfxbp_2.svg

sky130_fd_sc_hs__dfxbp_2