:cell:`sky130_fd_sc_hs__dfxbp`
==============================

**Delay flop, complementary outputs**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hs__dfxbp`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hs__dfxbp
-  **Library**: sky130_fd_sc_hs
-  **Inputs**:  2 (CLK, D)
-  **Outputs**: 2 (Q, Q_N)

:cell:`sky130_fd_sc_hs__dfxbp` symbols
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.. list-table:: 

    * - .. figure:: sky130_fd_sc_hs__dfxbp.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hs__dfxbp.pp.symbol.svg

:cell:`sky130_fd_sc_hs__dfxbp` schematic
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.. figure:: sky130_fd_sc_hs__dfxbp.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hs__dfxbp` GDSII layouts
--------------------------------------------



.. figure:: sky130_fd_sc_hs__dfxbp_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hs__dfxbp_1


.. figure:: sky130_fd_sc_hs__dfxbp_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hs__dfxbp_2