sky130_fd_sc_hs__clkdlyinv5sd1¶
Clock Delay Inverter 5-stage 0.15um length inner stage gate
This is a stub of cell description file
Cell name: sky130_fd_sc_hs__clkdlyinv5sd1
Type: cell
Verilog name: sky130_fd_sc_hs__clkdlyinv5sd1
Library: sky130_fd_sc_hs
Inputs: 1 (A)
Outputs: 1 (Y)