sky130_fd_sc_hdll__sdfxbp

Scan delay flop, non-inverted clock, complementary outputs

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hdll__sdfxbp

  • Type: cell

  • Verilog name: sky130_fd_sc_hdll__sdfxbp

  • Library: sky130_fd_sc_hdll

  • Inputs: 4 (CLK, D, SCD, SCE)

  • Outputs: 2 (Q, Q_N)

sky130_fd_sc_hdll__sdfxbp symbols

../../../../../_images/sky130_fd_sc_hdll__sdfxbp.symbol.svg
../../../../../_images/sky130_fd_sc_hdll__sdfxbp.pp.symbol.svg

sky130_fd_sc_hdll__sdfxbp schematic

../../../../../_images/sky130_fd_sc_hdll__sdfxbp.schematic.svg

sky130_fd_sc_hdll__sdfxbp GDSII layouts

../../../../../_images/sky130_fd_sc_hdll__sdfxbp_1.svg

sky130_fd_sc_hdll__sdfxbp_1

../../../../../_images/sky130_fd_sc_hdll__sdfxbp_2.svg

sky130_fd_sc_hdll__sdfxbp_2