:cell:`sky130_fd_sc_hdll__sdfxbp`
=================================

**Scan delay flop, non-inverted clock, complementary outputs**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hdll__sdfxbp`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hdll__sdfxbp
-  **Library**: sky130_fd_sc_hdll
-  **Inputs**:  4 (CLK, D, SCD, SCE)
-  **Outputs**: 2 (Q, Q_N)

:cell:`sky130_fd_sc_hdll__sdfxbp` symbols
-----------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_hdll__sdfxbp.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hdll__sdfxbp.pp.symbol.svg

:cell:`sky130_fd_sc_hdll__sdfxbp` schematic
-------------------------------------------

.. figure:: sky130_fd_sc_hdll__sdfxbp.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hdll__sdfxbp` GDSII layouts
-----------------------------------------------



.. figure:: sky130_fd_sc_hdll__sdfxbp_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__sdfxbp_1


.. figure:: sky130_fd_sc_hdll__sdfxbp_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__sdfxbp_2