sky130_fd_sc_hdll__or3¶
3-input OR
This is a stub of cell description file
Cell name: sky130_fd_sc_hdll__or3
Type: cell
Verilog name: sky130_fd_sc_hdll__or3
Library: sky130_fd_sc_hdll
Inputs: 3 (A, B, C)
Outputs: 1 (X)
3-input OR
This is a stub of cell description file
Cell name: sky130_fd_sc_hdll__or3
Type: cell
Verilog name: sky130_fd_sc_hdll__or3
Library: sky130_fd_sc_hdll
Inputs: 3 (A, B, C)
Outputs: 1 (X)