:cell:`sky130_fd_sc_hdll__or3`
==============================

**3-input OR**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hdll__or3`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hdll__or3
-  **Library**: sky130_fd_sc_hdll
-  **Inputs**:  3 (A, B, C)
-  **Outputs**: 1 (X)

:cell:`sky130_fd_sc_hdll__or3` symbols
--------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_hdll__or3.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hdll__or3.pp.symbol.svg

:cell:`sky130_fd_sc_hdll__or3` schematic
----------------------------------------

.. figure:: sky130_fd_sc_hdll__or3.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hdll__or3` GDSII layouts
--------------------------------------------



.. figure:: sky130_fd_sc_hdll__or3_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__or3_1


.. figure:: sky130_fd_sc_hdll__or3_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__or3_2


.. figure:: sky130_fd_sc_hdll__or3_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__or3_4