sky130_fd_sc_hdll__o2bb2a

2-input NAND and 2-input OR into 2-input AND

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hdll__o2bb2a

  • Type: cell

  • Verilog name: sky130_fd_sc_hdll__o2bb2a

  • Library: sky130_fd_sc_hdll

  • Inputs: 4 (A1_N, A2_N, B1, B2)

  • Outputs: 1 (X)

sky130_fd_sc_hdll__o2bb2a symbols

../../../../../_images/sky130_fd_sc_hdll__o2bb2a.symbol.svg
../../../../../_images/sky130_fd_sc_hdll__o2bb2a.pp.symbol.svg

sky130_fd_sc_hdll__o2bb2a schematic

../../../../../_images/sky130_fd_sc_hdll__o2bb2a.schematic.svg

sky130_fd_sc_hdll__o2bb2a GDSII layouts

../../../../../_images/sky130_fd_sc_hdll__o2bb2a_1.svg

sky130_fd_sc_hdll__o2bb2a_1

../../../../../_images/sky130_fd_sc_hdll__o2bb2a_2.svg

sky130_fd_sc_hdll__o2bb2a_2

../../../../../_images/sky130_fd_sc_hdll__o2bb2a_4.svg

sky130_fd_sc_hdll__o2bb2a_4