:cell:`sky130_fd_sc_hdll__o2bb2a`
=================================

**2-input NAND and 2-input OR into 2-input AND**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hdll__o2bb2a`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hdll__o2bb2a
-  **Library**: sky130_fd_sc_hdll
-  **Inputs**:  4 (A1_N, A2_N, B1, B2)
-  **Outputs**: 1 (X)

:cell:`sky130_fd_sc_hdll__o2bb2a` symbols
-----------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_hdll__o2bb2a.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hdll__o2bb2a.pp.symbol.svg

:cell:`sky130_fd_sc_hdll__o2bb2a` schematic
-------------------------------------------

.. figure:: sky130_fd_sc_hdll__o2bb2a.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hdll__o2bb2a` GDSII layouts
-----------------------------------------------



.. figure:: sky130_fd_sc_hdll__o2bb2a_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__o2bb2a_1


.. figure:: sky130_fd_sc_hdll__o2bb2a_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__o2bb2a_2


.. figure:: sky130_fd_sc_hdll__o2bb2a_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__o2bb2a_4