sky130_fd_sc_hdll__o21ba

2-input OR into first input of 2-input AND, 2nd input inverted

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hdll__o21ba

  • Type: cell

  • Verilog name: sky130_fd_sc_hdll__o21ba

  • Library: sky130_fd_sc_hdll

  • Inputs: 3 (A1, A2, B1_N)

  • Outputs: 1 (X)

sky130_fd_sc_hdll__o21ba symbols

../../../../../_images/sky130_fd_sc_hdll__o21ba.symbol.svg
../../../../../_images/sky130_fd_sc_hdll__o21ba.pp.symbol.svg

sky130_fd_sc_hdll__o21ba schematic

../../../../../_images/sky130_fd_sc_hdll__o21ba.schematic.svg

sky130_fd_sc_hdll__o21ba GDSII layouts

../../../../../_images/sky130_fd_sc_hdll__o21ba_1.svg

sky130_fd_sc_hdll__o21ba_1

../../../../../_images/sky130_fd_sc_hdll__o21ba_2.svg

sky130_fd_sc_hdll__o21ba_2

../../../../../_images/sky130_fd_sc_hdll__o21ba_4.svg

sky130_fd_sc_hdll__o21ba_4