sky130_fd_sc_hdll__clkmux2

Clock mux

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hdll__clkmux2

  • Type: cell

  • Verilog name: sky130_fd_sc_hdll__clkmux2

  • Library: sky130_fd_sc_hdll

  • Inputs: 3 (A0, A1, S)

  • Outputs: 1 (X)

sky130_fd_sc_hdll__clkmux2 symbols

../../../../../_images/sky130_fd_sc_hdll__clkmux2.symbol.svg
../../../../../_images/sky130_fd_sc_hdll__clkmux2.pp.symbol.svg

sky130_fd_sc_hdll__clkmux2 schematic

../../../../../_images/sky130_fd_sc_hdll__clkmux2.schematic.svg

sky130_fd_sc_hdll__clkmux2 GDSII layouts

../../../../../_images/sky130_fd_sc_hdll__clkmux2_1.svg

sky130_fd_sc_hdll__clkmux2_1

../../../../../_images/sky130_fd_sc_hdll__clkmux2_2.svg

sky130_fd_sc_hdll__clkmux2_2

../../../../../_images/sky130_fd_sc_hdll__clkmux2_4.svg

sky130_fd_sc_hdll__clkmux2_4