:cell:`sky130_fd_sc_hdll__clkmux2`
==================================

**Clock mux**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hdll__clkmux2`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hdll__clkmux2
-  **Library**: sky130_fd_sc_hdll
-  **Inputs**:  3 (A0, A1, S)
-  **Outputs**: 1 (X)

:cell:`sky130_fd_sc_hdll__clkmux2` symbols
------------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_hdll__clkmux2.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hdll__clkmux2.pp.symbol.svg

:cell:`sky130_fd_sc_hdll__clkmux2` schematic
--------------------------------------------

.. figure:: sky130_fd_sc_hdll__clkmux2.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hdll__clkmux2` GDSII layouts
------------------------------------------------



.. figure:: sky130_fd_sc_hdll__clkmux2_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__clkmux2_1


.. figure:: sky130_fd_sc_hdll__clkmux2_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__clkmux2_2


.. figure:: sky130_fd_sc_hdll__clkmux2_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__clkmux2_4