sky130_fd_sc_hdll__bufinv

Buffer followed by inverter

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hdll__bufinv

  • Type: cell

  • Verilog name: sky130_fd_sc_hdll__bufinv

  • Library: sky130_fd_sc_hdll

  • Inputs: 1 (A)

  • Outputs: 1 (Y)

sky130_fd_sc_hdll__bufinv symbols

../../../../../_images/sky130_fd_sc_hdll__bufinv.symbol.svg
../../../../../_images/sky130_fd_sc_hdll__bufinv.pp.symbol.svg

sky130_fd_sc_hdll__bufinv schematic

../../../../../_images/sky130_fd_sc_hdll__bufinv.schematic.svg

sky130_fd_sc_hdll__bufinv GDSII layouts

../../../../../_images/sky130_fd_sc_hdll__bufinv_16.svg

sky130_fd_sc_hdll__bufinv_16

../../../../../_images/sky130_fd_sc_hdll__bufinv_8.svg

sky130_fd_sc_hdll__bufinv_8