:cell:`sky130_fd_sc_hdll__bufinv`
=================================

**Buffer followed by inverter**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hdll__bufinv`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hdll__bufinv
-  **Library**: sky130_fd_sc_hdll
-  **Inputs**:  1 (A)
-  **Outputs**: 1 (Y)

:cell:`sky130_fd_sc_hdll__bufinv` symbols
-----------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_hdll__bufinv.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hdll__bufinv.pp.symbol.svg

:cell:`sky130_fd_sc_hdll__bufinv` schematic
-------------------------------------------

.. figure:: sky130_fd_sc_hdll__bufinv.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hdll__bufinv` GDSII layouts
-----------------------------------------------



.. figure:: sky130_fd_sc_hdll__bufinv_16.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__bufinv_16


.. figure:: sky130_fd_sc_hdll__bufinv_8.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__bufinv_8