sky130_fd_sc_hdll__and4bb¶
4-input AND, first two inputs inverted
This is a stub of cell description file
Cell name: sky130_fd_sc_hdll__and4bb
Type: cell
Verilog name: sky130_fd_sc_hdll__and4bb
Library: sky130_fd_sc_hdll
Inputs: 4 (A_N, B_N, C, D)
Outputs: 1 (X)