:cell:`sky130_fd_sc_hdll__and4bb`
=================================

**4-input AND, first two inputs inverted**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hdll__and4bb`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hdll__and4bb
-  **Library**: sky130_fd_sc_hdll
-  **Inputs**:  4 (A_N, B_N, C, D)
-  **Outputs**: 1 (X)

:cell:`sky130_fd_sc_hdll__and4bb` symbols
-----------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_hdll__and4bb.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hdll__and4bb.pp.symbol.svg

:cell:`sky130_fd_sc_hdll__and4bb` schematic
-------------------------------------------

.. figure:: sky130_fd_sc_hdll__and4bb.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hdll__and4bb` GDSII layouts
-----------------------------------------------



.. figure:: sky130_fd_sc_hdll__and4bb_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__and4bb_1


.. figure:: sky130_fd_sc_hdll__and4bb_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__and4bb_2


.. figure:: sky130_fd_sc_hdll__and4bb_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__and4bb_4