sky130_fd_sc_hdll__and3b¶
3-input AND, first input inverted
This is a stub of cell description file
Cell name: sky130_fd_sc_hdll__and3b
Type: cell
Verilog name: sky130_fd_sc_hdll__and3b
Library: sky130_fd_sc_hdll
Inputs: 3 (A_N, B, C)
Outputs: 1 (X)