:cell:`sky130_fd_sc_hdll__and3b`
================================

**3-input AND, first input inverted**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hdll__and3b`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hdll__and3b
-  **Library**: sky130_fd_sc_hdll
-  **Inputs**:  3 (A_N, B, C)
-  **Outputs**: 1 (X)

:cell:`sky130_fd_sc_hdll__and3b` symbols
----------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_hdll__and3b.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hdll__and3b.pp.symbol.svg

:cell:`sky130_fd_sc_hdll__and3b` schematic
------------------------------------------

.. figure:: sky130_fd_sc_hdll__and3b.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hdll__and3b` GDSII layouts
----------------------------------------------



.. figure:: sky130_fd_sc_hdll__and3b_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__and3b_1


.. figure:: sky130_fd_sc_hdll__and3b_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__and3b_2


.. figure:: sky130_fd_sc_hdll__and3b_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__and3b_4