sky130_fd_sc_hdll__and2b¶
2-input AND, first input inverted
This is a stub of cell description file
Cell name: sky130_fd_sc_hdll__and2b
Type: cell
Verilog name: sky130_fd_sc_hdll__and2b
Library: sky130_fd_sc_hdll
Inputs: 2 (A_N, B)
Outputs: 1 (X)
2-input AND, first input inverted
This is a stub of cell description file
Cell name: sky130_fd_sc_hdll__and2b
Type: cell
Verilog name: sky130_fd_sc_hdll__and2b
Library: sky130_fd_sc_hdll
Inputs: 2 (A_N, B)
Outputs: 1 (X)