sky130_fd_sc_hdll__a31o

3-input AND into first input of 2-input OR

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hdll__a31o

  • Type: cell

  • Verilog name: sky130_fd_sc_hdll__a31o

  • Library: sky130_fd_sc_hdll

  • Inputs: 4 (A1, A2, A3, B1)

  • Outputs: 1 (X)

sky130_fd_sc_hdll__a31o symbols

../../../../../_images/sky130_fd_sc_hdll__a31o.symbol.svg
../../../../../_images/sky130_fd_sc_hdll__a31o.pp.symbol.svg

sky130_fd_sc_hdll__a31o schematic

../../../../../_images/sky130_fd_sc_hdll__a31o.schematic.svg

sky130_fd_sc_hdll__a31o GDSII layouts

../../../../../_images/sky130_fd_sc_hdll__a31o_1.svg

sky130_fd_sc_hdll__a31o_1

../../../../../_images/sky130_fd_sc_hdll__a31o_2.svg

sky130_fd_sc_hdll__a31o_2

../../../../../_images/sky130_fd_sc_hdll__a31o_4.svg

sky130_fd_sc_hdll__a31o_4