sky130_fd_sc_hdll__a31o¶
3-input AND into first input of 2-input OR
This is a stub of cell description file
Cell name: sky130_fd_sc_hdll__a31o
Type: cell
Verilog name: sky130_fd_sc_hdll__a31o
Library: sky130_fd_sc_hdll
Inputs: 4 (A1, A2, A3, B1)
Outputs: 1 (X)