:cell:`sky130_fd_sc_hdll__a31o`
===============================

**3-input AND into first input of 2-input OR**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hdll__a31o`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hdll__a31o
-  **Library**: sky130_fd_sc_hdll
-  **Inputs**:  4 (A1, A2, A3, B1)
-  **Outputs**: 1 (X)

:cell:`sky130_fd_sc_hdll__a31o` symbols
---------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_hdll__a31o.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hdll__a31o.pp.symbol.svg

:cell:`sky130_fd_sc_hdll__a31o` schematic
-----------------------------------------

.. figure:: sky130_fd_sc_hdll__a31o.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hdll__a31o` GDSII layouts
---------------------------------------------



.. figure:: sky130_fd_sc_hdll__a31o_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__a31o_1


.. figure:: sky130_fd_sc_hdll__a31o_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__a31o_2


.. figure:: sky130_fd_sc_hdll__a31o_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hdll__a31o_4