sky130_fd_sc_hd__lpflow_clkinvkapwr

Clock tree inverter on keep-alive rail

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hd__lpflow_clkinvkapwr

  • Type: cell

  • Verilog name: sky130_fd_sc_hd__lpflow_clkinvkapwr

  • Library: sky130_fd_sc_hd

  • Inputs: 1 (A)

  • Outputs: 1 (Y)

sky130_fd_sc_hd__lpflow_clkinvkapwr symbols

../../../../../_images/sky130_fd_sc_hd__lpflow_clkinvkapwr.symbol.svg
../../../../../_images/sky130_fd_sc_hd__lpflow_clkinvkapwr.pp.symbol.svg

sky130_fd_sc_hd__lpflow_clkinvkapwr schematic

../../../../../_images/sky130_fd_sc_hd__lpflow_clkinvkapwr.schematic.svg

sky130_fd_sc_hd__lpflow_clkinvkapwr GDSII layouts

../../../../../_images/sky130_fd_sc_hd__lpflow_clkinvkapwr_1.svg

sky130_fd_sc_hd__lpflow_clkinvkapwr_1

../../../../../_images/sky130_fd_sc_hd__lpflow_clkinvkapwr_16.svg

sky130_fd_sc_hd__lpflow_clkinvkapwr_16

../../../../../_images/sky130_fd_sc_hd__lpflow_clkinvkapwr_2.svg

sky130_fd_sc_hd__lpflow_clkinvkapwr_2

../../../../../_images/sky130_fd_sc_hd__lpflow_clkinvkapwr_4.svg

sky130_fd_sc_hd__lpflow_clkinvkapwr_4

../../../../../_images/sky130_fd_sc_hd__lpflow_clkinvkapwr_8.svg

sky130_fd_sc_hd__lpflow_clkinvkapwr_8