sky130_fd_sc_hd__lpflow_clkinvkapwr¶
Clock tree inverter on keep-alive rail
This is a stub of cell description file
Cell name: sky130_fd_sc_hd__lpflow_clkinvkapwr
Type: cell
Verilog name: sky130_fd_sc_hd__lpflow_clkinvkapwr
Library: sky130_fd_sc_hd
Inputs: 1 (A)
Outputs: 1 (Y)