:cell:`sky130_fd_sc_hd__lpflow_clkinvkapwr`
===========================================

**Clock tree inverter on keep-alive rail**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hd__lpflow_clkinvkapwr`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hd__lpflow_clkinvkapwr
-  **Library**: sky130_fd_sc_hd
-  **Inputs**:  1 (A)
-  **Outputs**: 1 (Y)

:cell:`sky130_fd_sc_hd__lpflow_clkinvkapwr` symbols
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.. list-table:: 

    * - .. figure:: sky130_fd_sc_hd__lpflow_clkinvkapwr.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hd__lpflow_clkinvkapwr.pp.symbol.svg

:cell:`sky130_fd_sc_hd__lpflow_clkinvkapwr` schematic
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.. figure:: sky130_fd_sc_hd__lpflow_clkinvkapwr.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hd__lpflow_clkinvkapwr` GDSII layouts
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.. figure:: sky130_fd_sc_hd__lpflow_clkinvkapwr_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hd__lpflow_clkinvkapwr_1


.. figure:: sky130_fd_sc_hd__lpflow_clkinvkapwr_16.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hd__lpflow_clkinvkapwr_16


.. figure:: sky130_fd_sc_hd__lpflow_clkinvkapwr_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hd__lpflow_clkinvkapwr_2


.. figure:: sky130_fd_sc_hd__lpflow_clkinvkapwr_4.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hd__lpflow_clkinvkapwr_4


.. figure:: sky130_fd_sc_hd__lpflow_clkinvkapwr_8.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hd__lpflow_clkinvkapwr_8