sky130_fd_sc_hd__lpflow_clkbufkapwr¶
Clock tree buffer on keep-alive power rail
This is a stub of cell description file
Cell name: sky130_fd_sc_hd__lpflow_clkbufkapwr
Type: cell
Verilog name: sky130_fd_sc_hd__lpflow_clkbufkapwr
Library: sky130_fd_sc_hd
Inputs: 1 (A)
Outputs: 1 (X)