sky130_fd_sc_hd__dlygate4sd3

Delay Buffer 4-stage 0.50um length inner stage gates

This is a stub of cell description file

  • Cell name: sky130_fd_sc_hd__dlygate4sd3

  • Type: cell

  • Verilog name: sky130_fd_sc_hd__dlygate4sd3

  • Library: sky130_fd_sc_hd

  • Inputs: 1 (A)

  • Outputs: 1 (X)

sky130_fd_sc_hd__dlygate4sd3 symbols

../../../../../_images/sky130_fd_sc_hd__dlygate4sd3.symbol.svg
../../../../../_images/sky130_fd_sc_hd__dlygate4sd3.pp.symbol.svg

sky130_fd_sc_hd__dlygate4sd3 schematic

../../../../../_images/sky130_fd_sc_hd__dlygate4sd3.schematic.svg

sky130_fd_sc_hd__dlygate4sd3 GDSII layouts

../../../../../_images/sky130_fd_sc_hd__dlygate4sd3_1.svg

sky130_fd_sc_hd__dlygate4sd3_1