:cell:`sky130_fd_sc_hd__dlygate4sd3`
====================================

**Delay Buffer 4-stage 0.50um length inner stage gates**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hd__dlygate4sd3`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hd__dlygate4sd3
-  **Library**: sky130_fd_sc_hd
-  **Inputs**:  1 (A)
-  **Outputs**: 1 (X)

:cell:`sky130_fd_sc_hd__dlygate4sd3` symbols
--------------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_hd__dlygate4sd3.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hd__dlygate4sd3.pp.symbol.svg

:cell:`sky130_fd_sc_hd__dlygate4sd3` schematic
----------------------------------------------

.. figure:: sky130_fd_sc_hd__dlygate4sd3.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hd__dlygate4sd3` GDSII layouts
--------------------------------------------------



.. figure:: sky130_fd_sc_hd__dlygate4sd3_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hd__dlygate4sd3_1