sky130_fd_sc_hd__dfsbp¶
Delay flop, inverted set, complementary outputs
This is a stub of cell description file
Cell name: sky130_fd_sc_hd__dfsbp
Type: cell
Verilog name: sky130_fd_sc_hd__dfsbp
Library: sky130_fd_sc_hd
Inputs: 3 (CLK, D, SET_B)
Outputs: 2 (Q, Q_N)