:cell:`sky130_fd_sc_hd__dfsbp`
==============================

**Delay flop, inverted set, complementary outputs**

*This is a stub of cell description file*

-  **Cell name**: :cell:`sky130_fd_sc_hd__dfsbp`
-  **Type**: cell
-  **Verilog name**: sky130_fd_sc_hd__dfsbp
-  **Library**: sky130_fd_sc_hd
-  **Inputs**:  3 (CLK, D, SET_B)
-  **Outputs**: 2 (Q, Q_N)

:cell:`sky130_fd_sc_hd__dfsbp` symbols
--------------------------------------

.. list-table:: 

    * - .. figure:: sky130_fd_sc_hd__dfsbp.symbol.svg
      -
      - .. figure:: sky130_fd_sc_hd__dfsbp.pp.symbol.svg

:cell:`sky130_fd_sc_hd__dfsbp` schematic
----------------------------------------

.. figure:: sky130_fd_sc_hd__dfsbp.schematic.svg
    :align: center

:cell:`sky130_fd_sc_hd__dfsbp` GDSII layouts
--------------------------------------------



.. figure:: sky130_fd_sc_hd__dfsbp_1.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hd__dfsbp_1


.. figure:: sky130_fd_sc_hd__dfsbp_2.svg
    :align: center
    :width: 50%

    sky130_fd_sc_hd__dfsbp_2